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preliminary clock generator for intel ? calistoga chipset cy28443-2 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07718 rev. *b revised october 17, 2005 features ? supports intel ? pentium ? m cpu ? selectable cpu frequencies ? differential cpu clock pairs ? 100-mhz differential src clocks ? 48-mhz usb clock ? 96-mhz differential dot clock ? selectable 100-mhz lvds clock ? src clocks independently stoppable through clkreq#[a:b] ? 33-mhz pci clock ? low-voltage frequency select input ?i 2 c support with readback capabilities ? ideal lexmark spread spectrum profile for maximum electromagnetic interference (emi) reduction ? 3.3v power supply ? 56-pin package cpu src pci ref dot96 48m src/lvds100m x2 / x3 x5/6/7 x6 x 2 x 1 x 1 x1 pin configuration block diagram iref vdd ref[ 0: 1] vdd cput2_i tp/ srct11 cpuc2_i tp/ srcc11 vdd di vi der di vi der di vi der 14.318mhz cryst al cpu pll lvds pll fixed pll pll reference xi n xout pci_stp# fs[ c:a] vtt_pwrgd#/pd cput[0:1] cpuc[0:1] srct([2:5],[8:9]) vdd pci[3:5] vdd pcif[0:1] vdd_pci cpu_stp# clkreq[a:b]# vdd fctsel1 sel_clkreq itp_sel srcc([2:5],[8:9]) 48m vdd48 srct0/100mt_sst srcc0/100mc_sst i2c logic sdata sclk 27m non-spread vdd48 di vi der 27m pll 27m spread vdd48 vdd48 dot96t dot96c vdd 1 56 pci2/sel_clkreq vss 2 55 pci_stp# pci3 3 54 cpu_stp# pci4 4 53 ref0/fsc pci5/fctsel1 5 52 ref1/fctsel0 vss 6 51 vss vdd 7 50 xin itp_sel/pcif0 8 49 xout pcif1 9 48 vdd vtt_pwrgd#/ pd 10 47 sdata vdd 11 46 sclk fsa /48m 12 45 vss vss 13 44 cput0 dot96t/27m non spread 14 43 cpuc0 dot96c/27m spread 15 42 vdd fsb 16 41 cput1 srct0/100mt_sst 17 40 cpuc1 srcc0/100mc_sst 18 39 iref srct2 19 38 vssa srcc2 20 37 vdda vdd 21 36 srct11/ cput2_i tp srct3 22 35 srcc11/cpuc2_itp srcc3 23 34 vdd srct4 24 33 srct9/ clkreqa srcc4 25 32 srcc9/clkreqb srct5 _sata 26 31 srct8 srcc5_sata 27 30 srcc8 vdd 28 29 vss
preliminary cy28443-2 document #: 38-07718 rev. *b page 2 of 24 pin descriptions pin no. name type description 1, 7, 11, 21, 28, 34, 42, 48 vdd pwr 3.3v power supply 2, 6, 13, 29, 45, 51 vss gnd ground 33,32 srct9/clkreqa#, srcc9/clkreqb# i/o, pu 3.3v lvttl input for enabling assigned src clock (active low) or 100-mhz serial reference clock . default function is src9 3,4 pci[3:4] o, se 33-mhz clock 5 pci5/fctsel1 o, se 33-mhz clock/3.3 lvttl input for sel ecting src[t/c]0 or lvds100m[t/c] (sampled on the vtt_pwrgd# assertion). 8 itp_en/pcif0 i/o, se 3.3v lvttl input to enable src[t/c]7 or cpu[t/c]2_itp/33-mhz clock output . (sampled on the vtt_pwrgd# assertion). 9 pcif1 i/o, se 33-mhz clock 10 vtt_pwrgd#/pd i, pu 3.3v lvttl input . this pin is a level sensitive st robe used to latch the fs_[c:a], itp_en, fctsel[1:0], sel _clkreq. after vtt_pw rgd# (active low) assertion, this pin becomes a real-tim e input for asserting power-down (active high). 12 fsa/48m i/o 3.3v-tolerant input for cpu frequency selection/fixed 48-mhz clock output . 14, 15 dot96t/27m non spread dot96c/27m spread o, dif fixed 96-mhz differential clock/single-ended 27-mhz clocks . when configured for 27 mhz, only the clock on pin 15 contains spread. 16 fsb i 3.3v-tolerant in put for cpu frequency selection . 17,18 src[t/c]0/ lcd100m[t/c] o,dif 100-mhz differential serial reference clock/100-mhz lvds differential clock 19,20,22,23, 24,25,30,31 srct/c o, dif 100-mhz differential se rial reference clocks . 26,27 src[t/c]5_sata o, dif differential serial reference clock . recommended output for sata. 36,35 cput2_itp/srct11, cpuc2_itp/srcc11 o, dif selectable differential cpu or src clock output . 37 vdda pwr 3.3v power supply for pll . 38 vssa gnd ground for pll . 39 iref i a precision resistor is attached to this pin , which is connected to the internal current reference. 44,43,41,40 cpu[t/c ][0:1] o, dif differential cpu clock outputs . 46 sclk i smbus-compatible sclock . 47 sdata i/o smbus-compatible sdata . 49 xout o, se 14.318-mhz crystal output . 50 xin i 14.318-mhz crystal input . 52 ref1 o fixed 14.318-mhz clock output 53 ref0/fsc i/o 3.3v-tolerant input for cpu frequency selection/fixed 14.318 clock output . 54 cpu_stp# i, pu 3.3v lvttl input for cpu_stp# active low . 55 pci_stp# i, pu 3.3v lvttl input for pci_stp# active low . 56 pci2/sel_clkreq i/o, pd fixed 33-mhz clock output /3.3v-tolerant input for clkreq pin selection (sampled on the vtt_pwrgd# assertion). 0 = clkreq[a:b]# functionality 1 = src[t/c]9 functionality
preliminary cy28443-2 document #: 38-07718 rev. *b page 3 of 24 frequency select pins (fsa, fsb, and fsc) host clock frequency selection is achieved by applying the appropriate logic levels to fsa, fsb, fsc inputs prior to vtt_pwrgd# assertion (as seen by the clock synthesizer). upon vtt_pwrgd# being sampled low by the clock chip (indicating processor vtt voltage is stable), the clock chip samples the fsa, fsb, and fsc input values. for all logic levels of fsa, fsb, and fsc, vtt_pwrgd# employs a one-shot functionality in that once a valid low on vtt_pwrgd# has been sampled, all further vtt_pwrgd#, fsa, fsb, and fsc transitions will be ignored, except in test mode. serial data interface to enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. through the serial data interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. the registers associated with the serial data interface initializes to their default sett ing upon power-up, and therefore use of this interface is optional. clock device register changes are normally made upon system initialization, if any are required. the inte rface cannot be used during system operation for power management functions. data protocol the clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. for block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to st op after any complete byte has been transferred. for byte writ e and byte read operations, the system controller can access indi vidually indexed bytes. the offset of the indexed byte is encoded in the command code, as described in table 2 . the block write and block read protocol is outlined in table 3 while table 4 outlines the correspondi ng byte write and byte read protocol. the slave receiver address is 11010010 (d2h). table 1. frequency select table fsa, fsb and fsc fsc fsb fsa cpu src pcif/pci 27mhz ref0 dot96 usb 1 0 1 100 mhz 100 mhz 33 mhz 27 mhz 14.318 mhz 96 mhz 48 mhz 0 0 1 133 mhz 100 mhz 33 mhz 27 mhz 14.318 mhz 96 mhz 48 mhz 0 1 1 166 mhz 100 mhz 33 mhz 27 mhz 14.318 mhz 96 mhz 48 mhz 0 1 0 200 mhz 100 mhz 33 mhz 27 mhz 14.318 mhz 96 mhz 48 mhz table 2. command code definition bit description 7 0 = block read or block write operation, 1 = byte read or byte write operation (6:0) byte offset for byte read or byte write operation. fo r block read or block write operations, these bits should be '0000000' table 3. block read and block write protocol block write protocol block read protocol bit description bit description 1 start 1 start 8:2 slave address ? 7 bits 8:2 slave address ? 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code ? 8 bits 18:11 command code ? 8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 byte count ? 8 bits (skip this step if i 2 c_en bit set) 20 repeat start 28 acknowledge from slave 27:21 slave address ? 7 bits 36:29 data byte 1 ? 8 bits 28 read = 1 37 acknowledge from slave 29 acknowledge from slave 45:38 data byte 2 ? 8 bits 37:30 byte count from slave ? 8 bits 46 acknowledge from slave 38 acknowledge .... data byte /slave acknowledges 46:39 data byte 1 from slave ? 8 bits .... data byte n ?8 bits 47 acknowledge .... acknowledge from slave 55:48 data byte 2 from slave ? 8 bits
preliminary cy28443-2 document #: 38-07718 rev. *b page 4 of 24 .... stop 56 acknowledge .... data bytes from slave / acknowledge .... data byte n from slave ? 8 bits .... not acknowledge .... stop table 4. byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1start 1start 8:2 slave address ? 7 bits 8:2 slave address ? 7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code ? 8 bits 18:11 command code ? 8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 data byte ? 8 bits 20 repeated start 28 acknowledge from slave 27:21 slave address ? 7 bits 29 stop 28 read 29 acknowledge from slave 37:30 data from slave ? 8 bits 38 not acknowledge 39 stop table 3. block read and block write protocol (continued) block write protocol block read protocol bit description bit description
preliminary cy28443-2 document #: 38-07718 rev. *b page 5 of 24 control registers byte 0: control register 0 bit @pup name description 7 1 reserved reserved 6 1 reserved reserved 5 1 src[t/c]5 src[t/c]5 output enable 0 = disable (tri-state), 1 = enable 4 1 src[t/c]4 src[t/c]4 output enable 0 = disable (tri-state), 1 = enable 3 1 src[t/c]3 src[t/c]3 output enable 0 = disable (tri-state), 1 = enable 2 1 src[t/c]2 src[t/c]2 output enable 0 = disable (tri-state), 1 = enable 1 1 reserved reserved, set = 1 0 1 src[t/c]0 /100m[t/c]_sst src[t/c]0 /100m[t/c]_sst output enable 0 = disable (hi-z), 1 = enable byte 1: control register 1 bit @pup name description 7 1 pcif0 pcif0 output enable 0 = disabled, 1 = enabled 6 1 27m_nss_dot_96[t/c] 27m nonspread and dot_96 mhz output enable 0 = disable (tri-state), 1 = enabled 5 1 usb_48mhz usb_48m mhz output enable 0 = disabled, 1 = enabled 4 1 ref0 ref0 output enable 0 = disabled, 1 = enabled 3 1 ref1 ref1 output enable 0 = disabled, 1 = enabled 2 1 cpu[t/c]1 cpu[t/c]1 output enable 0 = disable (tri-state), 1 = enabled 1 1 cpu[t/c]0 cpu[t/c]0 output enable 0 = disable (tri-state), 1 = enabled 0 0 cpu, src, pci, pcif spread enable pll1 (cpu pll) spread spectrum enable 0 = spread off, 1 = spread on byte 2: control register 2 bit @pup name description 7 1 pci5 pci5 output enable 0 = disabled, 1 = enabled 6 1 pci4 pci4 output enable 0 = disabled, 1 = enabled 5 1 pci3 pci3 output enable 0 = disabled, 1 = enabled 4 1 pci2 pci2 output enable 0 = disabled, 1 = enabled 3 1 reserved reserved 2 1 reserved reserved 1 1 cpu[t/c]2 cpu[t/c]2 output enable 0 = disabled (hi-z), 1 = enabled 0 1 pcif1 pcif1 output enable 0 = disabled, 1 = enabled
preliminary cy28443-2 document #: 38-07718 rev. *b page 6 of 24 byte 3: control register 3 bit @pup name description 7 0 reserved reserved, set = 0 6 0 reserved reserved, set = 0 5 0 src5 allow control of src[t/c]5 with assertion of pci_st p# or sw pci_stp# 0 = free running, 1 = stopped with pci_stp# 4 0 src4 allow control of src[t/c]4 with assertion of pci_st p# or sw pci_stp# 0 = free running, 1 = stopped with pci_stp# 3 0 src3 allow control of src[t/c]3 with assertion of pci_st p# or sw pci_stp# 0 = free running, 1 = stopped with pci_stp# 2 0 src2 allow control of src[t/c]2 with assertion of pci_st p# or sw pci_stp# 0 = free running, 1 = stopped with pci_stp# 1 0 reserved reserved, set = 0 0 0 src0 allow control of src[t/c]0 with assertion of pci_st p# or sw pci_stp# 0 = free running, 1 = stopped with pci_stp# byte 4: control register 4 bit @pup name description 7 0 100m[t/c]_sst 100m[t/c]_sst pwrdwn drive mode 0 = driven in pwrdwn, 1 = tri-state 6 0 dot96[t/c] dot pwrdwn drive mode 0 = driven in pwrdwn, 1 = tri-state 5 1 src[t/c] src[t/c] stop dr ive mode when clkreq# asserted 0 = driven, 1 = tri-state 4 0 pcif1 allow control of pcif1 with assertion of sw and hw pci_stp# 0 = free running, 1 = stopped with pci_stp# 3 0 pcif0 allow control of pcif0 with assertion of sw and hw pci_stp# 0 = free running, 1 = stopped with pci_stp# 2 1 cpu[t/c]2 allow control of cpu[ t/c]2 with assert ion of cpu_stp# 0 = free running, 1 = stopped with cpu_stp# 1 1 cpu[t/c]1 allow control of cpu[ t/c]1 with assert ion of cpu_stp# 0 = free running, 1 = stopped with cpu_stp# 0 1 cpu[t/c]0 allow control of cpu[ t/c]0 with assert ion of cpu_stp# 0 = free running, 1 = stopped with cpu_stp# byte 5: control register 5 bit @pup name description 7 0 src[t/c] src[t/ c] stop drive mode 0 = driven when pci_stp# asserted, 1 = tri-state when pci_stp# asserted 6 0 cpu[t/c]2 cpu[t/c]2 stop drive mode 0 = driven when cpu_stp# asserted, 1 = tri-state when cpu_stp# asserted 5 0 cpu[t/c]1 cpu[t/c]1 stop drive mode 0 = driven when cpu_stp# asserted, 1 = tri-state when cpu_stp# asserted 4 0 cpu[t/c]0 cpu[t/c]0 stop drive mode 0 = driven when cpu_stp# asserted, 1 = tri-state when cpu_stp# asserted 3 0 src[t/c] src[t/c] pwrdwn drive mode 0 = driven when pd asserted, 1 = tri-state when pd asserted 2 0 cpu[t/c]2 cpu[t/c]2 pwrdwn drive mode 0 = driven when pd asserted, 1 = tri-state when pd asserted
preliminary cy28443-2 document #: 38-07718 rev. *b page 7 of 24 1 0 cpu[t/c]1 cpu[t/c]1 pwrdwn drive mode 0 = driven when pd asserted, 1 = tri-state when pd asserted 0 0 cpu[t/c]0 cpu[t/c]0 pwrdwn drive mode 0 = driven when pd asserted, 1 = tri-state when pd asserted byte 6: control register 6 bit @pup name description 7 0 test_sel ref/n or tri-state select 0 = tri-state, 1 = ref/n clock 6 0 test_mode test clo ck mode entry control 0 = normal operation, 1 = ref/n or tri-state mode, 5 1 ref1 ref0 output drive strength 0 = low, 1 = high 4 1 ref0 ref0 output drive strength 0 = low, 1 = high 3 1 pci, pcif and src clock outputs except those set to free running sw pci_stp function 0 = sw pci_stp assert, 1 = sw pci_stp deassert when this bit is set to 0, all stoppable pci, pcif, and src outputs will be stopped in a synchronous manner with no short pulses. when this bit is set to 1, all sto pped pci, pcif, and src outputs will resume in a synchronous manner with no short pulses. 2 hw fsc fsc reflects the value of the fsc pin sampled on power-up 0 = fsc was low during vtt_pwrgd# assertion 1 hw fsb fsb reflects the value of the fsb pin sampled on power-up 0 = fsb was low during vtt_pwrgd# assertion 0 hw fsa fsa reflects the value of the fsa pin sampled on power-up 0 = fsa was low during vtt_pwrgd# assertion byte 7: vendor id bit @pup name description 7 0 revision code bit 3 revision code bit 3 6 0 revision code bit 2 revision code bit 2 5 0 revision code bit 1 revision code bit 1 4 1 revision code bit 0 revision code bit 0 3 1 vendor id bit 3 vendor id bit 3 2 0 vendor id bit 2 vendor id bit 2 1 0 vendor id bit 1 vendor id bit 1 0 0 vendor id bit 0 vendor id bit 0 byte 8: control register 8 bit @pup name description 7 0 cpu_ss 0:?0.5% (peak to peak) 1: ?1.0% (peak to peak) 6 0 cpu-dwn_ss 0: down spread 1: center spread 5 0 reserved reserved, set = 0 4 0 reserved reserved, set = 0 3 0 reserved reserved, set = 0 2 1 48m 48-mhz output drive strength 0 = low, 1 = high byte 5: control register 5 (continued) bit @pup name description
preliminary cy28443-2 document #: 38-07718 rev. *b page 8 of 24 1 1 reserved reserved, set = 1 0 1 pcif0 33-mhz output drive strength 0 = low, 1 = high byte 8: control register 8 (continued) bit @pup name description byte 9: control register 9 bit @pup name description 70s3 27_96_100_ssc spread spectrum selection table: s[3:0] ss% ?0000? = ?0.5%(default value) ?0001? = ?1.0% ?0010? = ?1.5% ?0011? = ?2.0% ?0100? = 0.25% ?0101? = 0.5% ?0110? = 0.75% ?0111? = 1.0% ?1000? = ?0.35% ?1001? = ?0.68% ?1010? = ?1.09% ?1011? = ?1.425% ?1100? = 0.17% ?1101? = 0.34% ?1110? = 0.545% ?1111? = 0.712% 60s2 50s1 40s0 3 1 reserved reserved, set = 1 2 1 27m spread 27-mhz spread output enable 0 = disable (hi-z), 1 = enable 1 1 27m_ss/lcd100m spread enable 27m_ss/lcd100m spread spectrum enable. 0 = disable, 1 = enable. 0 1 pcif1 33-mhz output drive strength 0 = low, 1 = high byte 10: control register 10 bit @pup name description 7 1 src[t/c]11 src[t/c]11 output enable 0 = disable (hi-z), 1 = enable 6 1 src[t/c]9 src[t/c]9 output enable 0 = disable (hi-z), 1 = enable 5 1 reserved reserved, set = 1 4 1 src[t/c]8 src[t/c]8 output enable 0 = disable (hi-z), 1 = enable 3 0 src[t/c]9 allow control of src[t/ c]9 with assertion of sw pci_stp# 0 = free running, 1 = stopped with pci_stp# 2 0 src[t/c]11 allow control of src[t/ c]11 with assertio n of sw pci_stp# 0 = free running, 1 = stopped with pci_stp# 1 0 reserved reserved, set = 0 0 0 src[t/c]8 allow control of src[t/ c]8 with assertion of sw pci_stp# 0 = free running, 1 = stopped with pci_stp#
preliminary cy28443-2 document #: 38-07718 rev. *b page 9 of 24 byte 11: contro l register 11 bit @pup name description 7 0 reserved reserved set = 0 6 hw reserved reserved 5 hw reserved reserved 4 hw reserved reserved 3 0 27mhz 27 mhz (spread and non-spread) output drive strength 0 = low, 1 = high 2 0 reserved reserved set = 0 1 0 reserved reserved set = 0 0 hw reserved reserved byte 12: control register 12 bit @pup name description 7 0 clkreq#a clkreq#a enable 0 = disable 1 = enable 6 1 clkreq#b clkreq#b enable 0 = disable 1 = enable 5 1 reserved reserved 4 1 reserved reserved 3 1 reserved reserved 2 1 reserved reserved 1 1 reserved reserved 0 1 reserved reserved byte 13: control register 13 bit @pup name description 7 1 reserved reserved 6 1 96/100m clock speed 96/100 src clock speed 0 = 96 mhz 1 = 100 mhz 5 1 reserved reserved, set = 1 4 1 reserved reserved, set = 1 3 1 pci5 pci5 (spread and non-spread) output drive strength 0 = low, 1 = high 2 1 pci4 pci4 (spread and non-spread) output drive strength 0 = low, 1 = high 1 1 pci3 pci3 (spread and non-spread) output drive strength 0 = low, 1 = high 0 1 pci2 pci2 (spread and non-spread) output drive strength 0 = low, 1 = high byte 14: control register 14 bit @pup name description 7 1 reserved reserevd 6 0 reserved reserved 5 0 reserved reserved 4 0 clkreq#a src[t/c]5 control 0 = src[t/c]5 not st oppable by clkreq#a 1 = src[t/c]5 stoppable by clkreq#a
preliminary cy28443-2 document #: 38-07718 rev. *b page 10 of 24 the cy28443-2 requires a parallel resonance crystal. substituting a series resonance crystal will cause the cy28443-2 to operate at the wrong frequency and violate the ppm specification. for most ap plications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. crystal loading crystal loading plays a critical role in achieving low ppm perfor- mance. to realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appro- priate capacitive loading (cl). figure 1 shows a typical crystal configuration using the two trim capacitors. an important clarification for the following discussion is that the trim capa citors are in series with the crystal not parallel. it?s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. this is not true. 3 0 clkreq#a src[t/c]4 control 0 = src[t/c]4 not st oppable by clkreq#a 1 = src[t/c]4 stoppable by clkreq#a 2 0 clkreq#a src[t/c]3 control 0 = src[t/c]3 not st oppable by clkreq#a 1 = src[t/c]3 stoppable by clkreq#a 1 0 clkreq#a src[t/c]2 control 0 = src[t/c]2 not st oppable by clkreq#a 1 = src[t/c]2 stoppable by clkreq#a 0 0 clkreq#a src[t/c]1 control 0 = src[t/c]1 not st oppable by clkreq#a 1 = src[t/c]1 stoppable by clkreq#a byte 14: control register 14 (continued) bit @pup name description byte 15: control register 15 bit @pup name description 7 1 clkreq#b src[t/c]8 control 0 = src[t/c]8 not st oppable by clkreq#b 1 = src[t/c]8 stoppable by clkreq#b 6 0 reserved reserved 5 0 reserved reserved 4 0 clkreq#b src[t/c]5 control 0 = src[t/c]5 not st oppable by clkreq#b 1= src[t/c]5 stoppable by clkreq#b 3 0 clkreq#b src[t/c]4 control 0 = src[t/c]4 not st oppable by clkreq#b 1= src[t/c]4 stoppable by clkreq#b 2 0 clkreq#b src[t/c]3 control 0 = src[t/c]3 not st oppable by clkreq#b 1= src[t/c]3 stoppable by clkreq#b 1 0 clkreq#b src[t/c]2 control 0 = src[t/c]2 not st oppable by clkreq#b 1= src[t/c]2 stoppable by clkreq#b 0 0 clkreq#b src[t/c]1 control 0 = src[t/c]1 not st oppable by clkreq#b 1= src[t/c]1 stoppable by clkreq#b table 5. crystal recommendations frequency (fund) cut loading load cap drive (max.) shunt cap (max.) motional (max.) tolerance (max.) stability (max.) aging (max.) 14.31818 mhz at parallel 20 pf 0.1 mw 5 pf 0.016 pf 35 ppm 30 ppm 5 ppm
preliminary cy28443-2 document #: 38-07718 rev. *b page 11 of 24 calculating load capacitors in addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal load ing. as mentioned previously, the capacitance on each side of the crystal is in series with the crystal. this means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (cl). while the capacitance on each side of the crystal is in series with the crystal, trim capacitors (ce1,ce2) should be calculated to provide equal capacitive loading on both sides. use the following formulas to calculate the trim capacitor values for ce1 and ce2. cl ........................................... .........crystal load capacitance cle ............. .............. .............. actual loading seen by crystal using standard value trim capacitors ce ..................................................... external trim capacitors cs ........................................ ......stray capaci tance (terraced) ci .......................................................... internal capacitance (lead frame, bond wires etc.) clk_req[0:1]# description the clkreq#[a:b] signals are active low inputs used for clean enabling and disabling selected src outputs. the outputs controlled by clkreq#[a:b] are determined by the settings in register byte 8. the clkreq# signal is a de-bounced signal in that its state must remain unchanged during two consecutive rising edges of srcc to be recognized as a valid assertion or deassertion. (the assertion and deassertion of this signal is absolutely asynchronous.) clk_req[a:b]# assertion (clkreq# -> low) all differential outputs that were stopped are to resume normal operation in a glitch-free manner. the maximum latency from the assertion to active outputs is between 2?6 src clock periods (2 clocks are shown) with all src outputs resuming simultaneously. all stopped src outputs must be driven high within 10 ns of clkreq#[1:0] deassertion to a voltage greater than 200 mv. clk_req[a:b]# deassertion (clkreq# -> high) the impact of deasserting the clkreq#[a:b] pins is all src outputs that are set in the cont rol registers to stoppable via deassertion of clkreq#[a:b] are to be stopped after their next transition. the final st ate of all stopped dif signals is low, both srct clock and srcc clock outputs will not be driven. figure 1. crystal ca pacitive clarification xtal ce2 ce1 cs1 cs2 x1 x2 ci1 ci2 clock chip trace 2.8 pf trim 33 pf pin 3 to 6p figure 2. crystal loading example load capacitance (each side) total capacitance (as seen by the crystal) ce = 2 * cl ? (cs + ci) ce1 + cs1 + ci1 1 + ce2 + cs2 + ci2 1 ( ) 1 = cle figure 3. clk_req#[a:b] deassertion/assertion waveform srct(stoppable) srct(stoppable) srcc(free running) srct(free running) clkreq#x
preliminary cy28443-2 document #: 38-07718 rev. *b page 12 of 24 pd (power-down) clarification the vtt_pwrgd# /pd pin is a dual-function pin. during initial power-up, the pin functions as vtt_pwrgd#. once vtt_pwrgd# has been sampled low by the clock chip, the pin assumes pd functionality. the pd pin is an asynchronous active high input used to shut off all clocks cleanly prior to shutting off power to the devi ce. this signal is synchronized internal to the device prior to powering down the clock synthe- sizer. pd is also an asynchronous input for powering up the system. when pd is asserted high, all clocks need to be driven to a low value and held prior to turning off the vcos and the crystal oscillator. pd (power-down) assertion when pd is sampled high by two consecutive rising edges of cpuc, all single-ended outputs will be held low on their next high-to-low transition and di fferential clocks must held high or tri-stated (depending on the state of the control register drive mode bit) on the next diff clock# high-to-low transition within 4 clock periods. when the smbus pd drive mode bit corresponding to the differential (cpu, src, and dot) clock output of interest is programme d to ?0?, the clock output are held with ?diff clock? pin driven high at 2 x iref, and ?diff clock#? tristate. if the control register pd drive mode bit corresponding to the output of interest is programmed to ?1?, then both the ?diff clock? and the ?diff cl ock#? are tri-state. note figure 4 shows cput = 133 mhz and pd drive mode = ?1? for all differ- ential outputs. this diagram and description is applicable to valid cpu frequencies 100, 133, 166, and 200 mhz. in the event that pd mode is desired as the initial power-on state, pd must be asserted high in less than 10 s after asserting vtt_pwrgd#. it should be noted that 96_100_ssc will follow the dot waveform is selected for 96 mhz and the src waveform when in 100-mhz mode. pd deassertion the power-up latency is less than 1.8 ms. this is the time from the deassertion of the pd pin or the ramping of the power supply until the time that stab le clocks are output from the clock chip. all differential outputs stopped in a three-state condition resulting from power down will be driven high in less than 300 s of pd deassertion to a voltage greater than 200 mv. after the clock chip?s internal pll is powered up and locked, all outputs will be enabled within a few clock cycles of each other. figure 5 is an example showing the relationship of clocks coming up. it should be noted that 96_100_ssc will follow the dot waveform is selected for 96 mhz and the src waveform when in 100-mhz mode. figure 4. power-down assertion timing waveform pd usb, 48mhz dot96t dot96c srct 100mhz srcc 100mhz cput, 133mhz pci, 33 mhz ref cpuc, 133mhz figure 5. power-down deassertion timing waveform dot96c pd cpuc, 133mhz cput, 133mhz srcc 100mhz usb, 48mhz dot96t srct 100mhz tstable <1.8 ms pci, 33mhz ref tdrive_pwrdn# <300 s, >200 mv
preliminary cy28443-2 document #: 38-07718 rev. *b page 13 of 24 cpu_stp# assertion the cpu_stp# signal is an active low input used for synchronous stopping and starting the cpu output clocks while the rest of the clock generator continues to function. when the cpu_stp# pin is asse rted, all cpu outputs that are set with the smbus configuration to be stoppable via assertion of cpu_stp# will be stopped within two?six cpu clock periods after being sampled by two rising edges of the internal cpuc clock. the final states of the stopped cpu signals are cput = high and cpuc = low. there is no change to the output drive current values du ring the stopped state. the cput is driven high with a current value equal to 6 x (iref), and the cpuc signal will be tri-stated. cpu_stp# deassertion the deassertion of the cpu_stp# signal will cause all cpu outputs that were stopped to resume normal operation in a synchronous manner. synchronous manner meaning that no short or stretched clock pulses will be produce when the clock resumes. the maximum latency from the deassertion to active outputs is no more than two cpu clock cycles. cpu_stp# cput cpuc figure 6. cpu_stp# assertion waveform cpu_stp# cput cpuc cput internal tdrive_cpu_stp#,10 ns > 200 mv cpuc internal figure 7. cpu_stp# deassertion waveform dot96c dot96t cpuc(stoppable) cput(stoppable) cpuc(free running cput(free running pd 1.8 ms cpu_stop# figure 8. cpu_stp#= driven, cp u_pd = driven, dot_pd = driven
preliminary cy28443-2 document #: 38-07718 rev. *b page 14 of 24 pci_stp# assertion the pci_stp# signal is an active low input used for synchronous stopping and starting the pci outputs while the rest of the clock generator co ntinues to function. the set-up time for capturing pci_stp# going low is 10 ns (t su ). (see figure 10 .) the pcif clocks will not be affected by this pin if their corresponding control bit in the smbus register is set to allow them to be free running. pci_stp# deassertion the deassertion of the pci_stp# signal will cause all pci and stoppable pcif clocks to resume running in a synchronous manner within two pci clock periods after pci_stp# transi- tions to a high level. dot96c dot96t cpuc(stoppable) cput(stoppable) cpuc(free running) cput(free running) pd 1.8 ms cpu_stop# figure 9. cpu_stp# = tri-state, cpu_ pd = tri-state, dot_pd = tri-state tsu pci_stp# pci_f pci src 100mhz figure 10. pci_stp# assertion waveform pci_stp# pci_f pci src 100mhz tsu tdrive_src figure 11. pci_stp# deassertion waveform
preliminary cy28443-2 document #: 38-07718 rev. *b page 15 of 24 fs_a, fs_b,fs_c vtt_pwrgd# pwrgd_vrm vdd clock gen clock state clock outputs clock vco 0.2-0.3 ms delay state 0 state 2 state 3 wait for vtt_pwrgd# sample sels off off on on state 1 device is not affected, vtt_pwrgd# is ignored figure 12. vtt_pwrgd# timing diagram vtt_pwrgd# = low delay >0.25 ms s1 power off s0 vdd_a = 2.0v sample inputs straps s2 normal operation wait for <1.8ms enable outputs s3 vtt_pwrgd# = toggle vdd_a = off figure 13. clock generator power-up/run state diagram
preliminary cy28443-2 document #: 38-07718 rev. *b page 16 of 24 1 absolute maximum conditions parameter description condition min. max. unit v dd core supply voltage ?0.5 4.6 v v dd_a analog supply voltage ?0.5 4.6 v v in input voltage relative to v ss ?0.5 v dd + 0.5 vdc t s temperature, storage non-functional ?65 150 c t a temperature, operating ambient functional 0 85 c t j temperature, junction functional ? 150 c ? jc dissipation, junction to case mil-std-883e method 1012.1 ? 20 c/w ? ja dissipation, junction to ambient jedec (jesd 51) ? 60 c/w esd hbm esd protection (human body model) mil-std-883, method 3015 2000 ? v ul-94 flammability rating at 1/8 in. v?0 msl moisture sensitivity level 1 multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supp ly sequencing is not required. dc electrical specifications parameter description condition min. max. unit all vdd?s 3.3v operating voltage 3.3 5% 3.135 3.465 v v ili2c input low voltage sdata, sclk ? 1.0 v v ihi2c input high voltage sdata, sclk 2.2 ? v v il_fs fs_[a,b] input low voltage v ss ? 0.3 0.35 v v ih_fs fs_[a,b] input high voltage 0.7 v dd + 0.5 v v ilfs_c fs_c input low voltage v ss ? 0.3 0.35 v v imfs_c fs_c input middle voltage typical 0.7 1.7 v v ihfs_c fs_c input high voltage typical 2.0 v dd + 0.5 v v il 3.3v input low voltage v ss ? 0.3 0.8 v v ih 3.3v input high voltage 2.0 v dd + 0.3 v i il input low leakage current except internal pull-up resistors, 0 < v in < v dd ?5 5 a i ih input high leakage current except internal pull-down resistors, 0 < v in < v dd ?5 a v ol 3.3v output low voltage i ol = 1 ma ? 0.4 v v oh 3.3v output high voltage i oh = ?1 ma 2.4 ? v i oz high-impedance output current ?10 10 a c in input pin capacitance 3 5 pf c out output pin capacitance 3 6 pf l in pin inductance ? 7 nh v xih xin high voltage 0.7v dd v dd v v xil xin low voltage 0 0.3v dd v i dd3.3v dynamic supply current at max. load and freq. per figure 16 ? 300 ma i pd3.3v power-down supply current pd asserted, outputs driven ? 70 ma i pd3.3v power-down supply current pd asserted, outputs tri-state ? 5 ma
preliminary cy28443-2 document #: 38-07718 rev. *b page 17 of 24 ac electrical specifications parameter description condition min. max. unit crystal t dc xin duty cycle the device will operate reliably with input duty cycles up to 30/ 70 but the ref clock duty cycle will not be within specification 47.5 52.5 % t period xin period when xin is driven from an external clock source 69.841 71.0 ns t r / t f xin rise and fall times measured between 0.3v dd and 0.7v dd ?10.0ns t ccj xin cycle to cycle jitter as an average over 1- s duration ? 500 ps l acc long-term accuracy measured at crossing point v ox ? 300 ppm cpu at 0.7v t dc cput and cpuc duty cycle measured at crossing point v ox 45 55 % t period 100-mhz cput and cpuc period measured at crossing point v ox 9.997001 10.00300 ns t period 133-mhz cput and cpuc period measured at crossing point v ox 7.497751 7.502251 ns t period 166-mhz cput and cpuc period measured at crossing point v ox 5.998201 6.001801 ns t period 200-mhz cput and cpuc period measured at crossing point v ox 4.998500 5.001500 ns t periodss 100-mhz cput and cpuc period, ssc measured at crossing point v ox 9.997001 10.05327 ns t periodss 133-mhz cput and cpuc period, ssc measured at crossing point v ox 7.497751 7.539950 ns t periodss 166-mhz cput and cpuc period, ssc measured at crossing point v ox 5.998201 6.031960 ns t periodss 200-mhz cput and cpuc period, ssc measured at crossing point v ox 4.998500 5.026634 ns t periodabs 100-mhz cput and cpuc absolute period measured at crossing point v ox 9.912001 10.08800 ns t periodabs 133-mhz cput and cpuc absolute period measured at crossing point v ox 7.412751 7.587251 ns t periodabs 166-mhz cput and cpuc absolute period measured at crossing point v ox 5.913201 6.086801 ns t periodabs 200-mhz cput and cpuc absolute period measured at crossing point v ox 4.913500 5.086500 ns t periodssabs 100-mhz cput and cpuc absolute period, ssc measured at crossing point v ox 9.912001 10.13827 ns t periodssabs 133-mhz cput and cpuc absolute period, ssc measured at crossing point v ox 7.412751 7.624950 ns t periodssabs 166-mhz cput and cpuc absolute period, ssc measured at crossing point v ox 5.913201 6.116960 ns t periodssabs 200-mhz cput and cpuc absolute period, ssc measured at crossing point v ox 4.913500 5.111634 ns t ccj cput/c cycle to cycle jitter measured at crossing point v ox ?85 [1] ps t ccj2 cpu2_itp cycle to cycle jitter measured at crossing point v ox ?125 [1] ps l acc long-term accuracy measured at crossing point v ox ? 300 ppm t skew cpu1 to cpu0 clock skew measured at crossing point v ox ? 100 ps t skew2 cpu2_itp to cpu0 clock skew measured at crossing point v ox ? 150 ps t r / t f cput and cpuc rise and fall time measured from v ol = 0.175 to v oh = 0.525v 175 700 ps t rfm rise/fall matching determined as a fraction of 2*(t r ? t f )/(t r + t f ) ?20% ? t r rise time variation ? 125 ps ? t f fall time variation ? 125 ps note: 1. measured with one ref on.
preliminary cy28443-2 document #: 38-07718 rev. *b page 18 of 24 v high voltage high math averages figure 16 660 850 mv v low voltage low math averages figure 16 ?150 ? mv v ox crossing point voltage at 0.7v swing 250 550 mv v ovs maximum overshoot voltage ? v high + 0.3 v v uds minimum undershoot voltage ?0.3 ? v v rb ring back voltage see figure 16 . measure se ? 0.2 v src at 0.7v t dc srct and srcc duty cycle measured at crossing point v ox 45 55 % t period 100-mhz srct and srcc period measured at crossing point v ox 9.997001 10.00300 ns t periodss 100-mhz srct and srcc period, ssc measured at crossing point v ox 9.997001 10.05327 ns t periodabs 100-mhz srct and srcc absolute period measured at crossing point v ox 9.872001 10.12800 ns t periodssabs 100-mhz srct and srcc absolute period, ssc measured at crossing point v ox 9.872001 10.17827 ns t skew any srct/c to srct/c clock skew measured at crossing point v ox ? 250 ps t ccj srct/c cycle to cycle jitter measured at crossing point v ox ?125 [1] ps l acc srct/c long term accuracy measured at crossing point v ox ? 300 ppm t r / t f srct and srcc rise and fall time measured from v ol = 0.175 to v oh = 0.525v 175 700 ps t rfm rise/fall matching determined as a fraction of 2*(t r ? t f )/(t r + t f ) ?20% ? t r rise timevariation ? 125 ps ? t f fall time variation ? 125 ps v high voltage high math averages figure 16 660 850 mv v low voltage low math averages figure 16 ?150 ? mv v ox crossing point voltage at 0.7v swing 250 550 mv v ovs maximum overshoot voltage ? v high + 0.3 v v uds minimum undershoot voltage ?0.3 ? v v rb ring back voltage see figure 16. measure se ? 0.2 v 96_100_ssc/src0 at 0.7v t dc ssct and sscc duty cycle measured at crossing point v ox 45 55 % t period 100-mhz ssct and sscc period measured at crossing point v ox 9.997001 10.00300 ns t periodss 100-mhz ssct and sscc period, ssc measured at crossing point v ox 9.997001 10.05327 ns t periodabs 100-mhz ssct and sscc absolute period measured at crossing point v ox 9.872001 10.12800 ns t periodssabs 100-mhz srct and srcc absolute period, ssc measured at crossing point v ox 9.872001 10.17827 ns t period 96-mhz ssct and sscc period measured at crossing point v ox 10.41354 10.41979 ns t periodss 96-mhz ssct and sscc period, ssc measured at crossing point v ox 10.41354 10.47215 ns t periodabs 96-mhz ssct and sscc absolute period measured at crossing point v ox 10.16354 10.66979 ns t periodssabs 96-mhz srct and srcc absolute period, ssc measured at crossing point v ox 10.16354 10.72266 ns t ccj ssct/c cycle to cycle jitter measured at crossing point v ox ? 140 ps l acc ssct/c long term accuracy measured at crossing point v ox ? 300 ppm ac electrical specifications (continued) parameter description condition min. max. unit
preliminary cy28443-2 document #: 38-07718 rev. *b page 19 of 24 t r / t f ssct and sscc rise and fall time measured from v ol = 0.175 to v oh = 0.525v 175 700 ps t rfm rise/fall matching determined as a fraction of 2*(t r ? t f )/(t r + t f ) ?20% ? t r rise timevariation ? 125 ps ? t f fall time variation ? 125 ps v high voltage high math averages figure 16 660 850 mv v low voltage low math averages figure 16 ?150 ? mv v ox crossing point voltage at 0.7v swing 250 550 mv v ovs maximum overshoot voltage ? v high + 0.3 v v uds minimum undershoot voltage ?0.3 ? v v rb ring back voltage see figure 16. measure se ? 0.2 v pci/pcif at 3.3v t dc pci duty cycle measurement at 1.5v 45 55 % t period spread disabled pcif/pci period m easurement at 1.5v 29.99100 30.00900 ns t periodss spread enabled pcif/pci period, ssc measurement at 1. 5v 29.9910 30.15980 ns t periodabs spread disabled pcif/pci period m easurement at 1.5v 29.49100 30.50900 ns t periodssabs spread enabled pcif/pci period, ssc measurement at 1. 5v 29.49100 30.65980 ns t high pcif and pci high time measurement at 2.4v 12.0 ? ns t low pcif and pci low time measurement at 0.4v 12.0 ? ns t r / t f pcif/pci rising and falling edge rate m easured between 0.8v and 2.0v 1.0 4.0 v/ns t skew any pci clock to any pci clock skew measurement at 1.5v ? 500 ps t ccj pcif and pci cycle to cycle jitter measurement at 1.5v ? 500 [2] ps l acc pcif/pci long term accuracy measured at crossing point v ox ? 300 ppm dot96 at 0.7v t dc dot96t and dot96c duty cycle measured at crossing point v ox 45 55 % t period dot96t and dot96c period measured at crossing point v ox 10.41354 10.41979 ns t periodabs dot96t and dot96c absolute period measured at crossing point v ox 10.16354 10.66979 ns t ccj dot96t/c cycle to cycle jitter measured at crossing point v ox ? 250 ps l acc dot96t/c long term accuracy measured at crossing point v ox ? 300 ppm t r / t f dot96t and dot96c rise and fall time measured from v ol = 0.175 to v oh = 0.525v 175 700 ps t rfm rise/fall matching determined as a fraction of 2*(t r ? t f )/(t r + t f ) ?20% ? t r rise time variation ? 125 ps ? t f fall time variation ? 125 ps v high voltage high math averages figure 16 660 850 mv v low voltage low math averages figure 16 ?150 ? mv v ox crossing point voltage at 0.7v swing 250 550 mv v ovs maximum overshoot voltage ? v high + 0.3 v v uds minimum undershoot voltage ?0.3 ? v v rb ring back voltage see figure 16. measure se ? 0.2 v note: 2. measured in low drive mode. ac electrical specifications (continued) parameter description condition min. max. unit
preliminary cy28443-2 document #: 38-07718 rev. *b page 20 of 24 48_m at 3.3v t dc duty cycle measurement at 1.5v 45 55 % t period period measurement at 1.5v 20.83125 20.83542 ns t periodabs absolute period measurement at 1.5v 20.48125 21.18542 ns t high 48_m high time measurement at 2.4v 8.094 11.200 ns t low 48_m low time measurement at 0.4v 7.694 11.500 ns t r / t f rising and falling edge rate measured between 0.8v and 2.0v 1.0 2.0 v/ns t ccj cycle to cycle jitter measurement at 1.5v ? 350 ps l acc 48m long term accuracy measured at crossing point v ox ? 100 ppm 27_m at 3.3v t dc duty cycle measurement at 1.5v 45 55 % t period spread disabled 27m period meas urement at 1.5v 27.000 27.0547 ns spread enabled 27m period measurement at 1.5v 27.000 27.0547 t high 27_m high time measurement at 2.0v 10.5 ? ns t low 27_m low time measurement at 0.8v 10.5 ? ns t r / t f rising and falling edge rate measured between 0.8v and 2.0v 1.0 4.4 v/ns t ccj cycle to cycle jitter measurement at 1.5v ? 520 ps l acc 27_m long term accuracy measured at crossing point v ox ? 0 ppm ref at 3.3v t dc ref duty cycle measurement at 1.5v 45 55 % t period ref period measurement at 1.5v 69.8203 69.8622 ns t periodabs ref absolute period measurem ent at 1.5v 68.82033 70.86224 ns t r / t f ref rising and falling edge rate meas ured between 0.8v and 2.0v 1.0 4.0 v/ns t skew ref clock to ref clock measurement at 1.5v ? 500 ps t ccj ref cycle to cycle jitter measurement at 1.5v ? 1000 ps l acc long term accuracy measurement at 1.5v ? 300 ppm enable/disable and set-up t stable clock stabilization from power-up ? 1.8 ms t ss stopclock set-up time 10.0 ? ns ac electrical specifications (continued) parameter description condition min. max. unit
preliminary cy28443-2 document #: 38-07718 rev. *b page 21 of 24 test and measurement set-up for pci single-ended signals and reference the following diagram shows test load configurations for the single-ended pci, usb, and ref output signals. the following diagram shows the test load configuration for the differential cpu and src outputs. pci/ usb ref 33 ? measurement point 5 pf 60 ? 12 ? measurement point 5 pf 60 ? 12 ? measurement point 5 pf 60 ? figure 14.single-ended load configuration low drive option pci/ usb ref 12 ? measurement point 5 pf 60 ? 12 ? measurement point 5 pf 60 ? 12 ? measurement point 5 pf 60 ? 12 ? measurement point 5 pf 60 ? 12 ? measurement point 5 pf 60 ? figure 15. single-ended load configuration high drive option cput cpuc 33 ? 33 ? 49.9 ? 49.9 ? m easurem ent point 2 pf 475 ? ir e f m easurem ent point 2 pf srct srcc 100 ? differential dot96t dot96c 96_100_ssct 96_100_sscc figure 16. 0.7v differential load configuration
preliminary cy28443-2 document #: 38-07718 rev. *b page 22 of 24 2.4v 0.4v 3.3v 0v t r t f 1.5v 3.3v si g nals t dc - - figure 17. single-ended output si gnals (for ac parameters measurement) ordering information part number package type product flow lead-free cy28443oxc-2 56-pin ssop commercial, 0 to 85 c cy28443oxc-2t 56-pin ssop ? tape and reel commercial, 0 to 85 c cy28443zxc-2 56-pin tssop commercial, 0 to 85 c CY28443ZXC-2T 56-pin tssop ? tape and reel commercial, 0 to 85 c
preliminary cy28443-2 document #: 38-07718 rev. *b page 23 of 24 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. purchase of i 2 c components from cypress or one of its sublicensed as sociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided t hat the system conforms to the i 2 c standard specification as defined by philips. intel and pentium are registered trademar ks of intel corporation. all pr oduct and company names mentione d in this document are the trademar ks of their respective holders. intel and pent ium are registered trademarks of intel corporati on. all product and company names ment ioned in this document are trademarks of their respective holders. package diagrams seating plane 1 bsc 0-8 max. gauge plane 28 29 56 1.100[0.043] 0.051[0.002] 0.851[0.033] 0.508[0.020] 0.249[0.009] 7.950[0.313] 0.25[0.010] 6.198[0.244] 13.894[0.547] 8.255[0.325] 5.994[0.236] 0.950[0.037] 0.500[0.020] 14.097[0.555] 0.152[0.006] 0.762[0.030] dimensions in mm[inches] min. max. 0.170[0.006] 0.279[0.011] 0.20[0.008] 0.100[0.003] 0.200[0.008] reference jedec mo-153 package weight 0.42gms part # z5624 standard pkg. zz5624 lead free pkg. 56-lead thin shrunk small outline package, type ii (6 mm x 12 mm) z56 51-85060-*c 0.095 0.025 0.008 seating plane 0.420 0.088 .020 0.292 0.299 0.395 0.092 bsc 0.110 0.016 0.720 0.008 0.0135 0.730 dimensions in inches min. max. 0.040 0.024 0-8 gauge plane .010 1 28 56 29 0.110 0.005 0.010 51-85062-*c 56-lead shrunk small outline package o56
preliminary cy28443-2 document #: 38-07718 rev. *b page 24 of 24 document history page document title: cy28443-2 clock generator for intel ? calistoga chipset document number: 38-07718 rev. ecn no. issue date orig. of change description of change ** 285670 see ecn rgl new data sheet *a 318716 see ecn rgl corrected the register m appings to reflect the changes in eros *b 402316 see ecn rgl/xlz change the document status to preliminary update register table add figure 15 and 16 for single-ended load configuration update dc electrical specification table update ac electrical specification table

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